Output of this phase interpolator is driven to the next repeater as depicted in Fig. 4.1. The interpolating between the two signals results in the summation of the FIR shown in Fig. 4.1. The phase interpolator weighting adjustment represents the FIR filter coefficient, and the transfer function is given by H = α + z −1 . The added phase interpolator has very little power and area cost and allows programmable α. With a programmable interpolator, the filter function can be adjusted. An α of zero passes the MDLL divided clock to the output, and an α of one forwards the reference clock like a simple buffer. Tuning the phase interpolator setting, α, changes the -3dB bandwidth. Fig. 3.15 shows the cascade of two clock repeaters with FIR filtering for the output clock. The phase noise side-band spectrum of two cascaded clock repeaters with 40% FIR interpolation coefficient is shown in Fig. 4.2. Jitter is reduced with each stage of the filtering. Since each stage can have the filtering coefficient independently adjusted, Fig. 4.3 illustrates the impact of varying α for each of 4 cascaded clock repeaters. The best combination for least jitter is found to be an α of 40% for the first 3 repeaters and an α of 0.6 in the fourth repeater. Proper choice can reduces jitter by up to 50% in a repeater stage. In our system where more repeaters are used, additional stages of FIR filtering do not reduce jitter significantly due the sharp roll-off of filtering beyond a fourth-order filter. MDLL input mux is implemented as a configurable phase interpolator, shown in Fig. 4.4, to change the relative injection strengths of the reference edge and the VCO feedback edge. It can be configured from 0 to 100% injection strength with 20% steps. Where 0%setting denotes the mux is configured to operate as a normal delay cell in the VCO, thus the CMU is configured as a PLL. A 100% setting permits full injection of reference edge, thus CMU is configured as an MDLL. Intermediate settings interpolate between reference and VCO edges,how to dry cannabis and the CMU operates as a semi-PLL/MDLL. At the output of the CMU we are adding a second mux/phase interpolator structure that takes the incoming reference clockand a divided version of the CMU as inputs.

Output of this phase interpolator goes directly to the clock driver, as depicted in Fig. 4.1. With such configurability, jitter accumulation across the different repeaters can be kept low. depending on its location on the cable. Early on in the link, when forward clock is still clean and didn’t suffer jitter accumulation, the CMU is configured in a MDLL mode to reset VCO jitter accumulation. We also set the PI to forward the incoming clock to the next stage, as depicted in Fig. 4.5. Similarly, later on the link, when clock has undergone significant jitter accumulation, we tune the CMU in a PLL mode to filter incoming clock jitter. We also set the PI to forward a divided version of the filtered PLL clock, Fig. 4.5. Intermediate settings can be used in the middle of the cable link. Multiplying DLLs have gained much interest in recent publications because of their inherent ability to reset jitter accumulation inside the VCOs compared to MPLLs. This is attributed to the fact that reference clock edges are injected into the VCO each reference cycle and thus remove the jitter accumulation memory of the VCO. This can be interpreted as designing an MPLL that has a bandwidth equivalent to the reference frequency bandwidth, compared to traditional MPLLs where bandwidth can’t be greater than one tenth of the reference frequency. One challenging aspect in the design of MDLLs is the alignment of the injected reference edge to the VCO feedback signal. As shown in Fig. 4.6, the select logic is responsible for generating an aperture that allows the reference edge inside the loop and blocks the VCO feedback signal. As shown in Fig. 4.6, any delay mismatch between the reference edge and the VCO feedback edge, or a mismatch in the charge pump would cause the pulse following the injected edge different than the remaining VCO pulses, an effect that would manifest itself as period jitter or reference spur in the frequency domain, which limits the minimum jitter attained by the MDLL. Solutions are provided to this problem in literature. In a slave oscillator is injected with the MDLL master oscillator.

The slave oscillator acts as a LPF for the period jitter. In an auxiliary calibration loop is used to measure the duty cycle error of the output. This error is then used to unbalance the charge pump current to absorb this mismatch. In digital duty cycle measurements are correlated between consecutive samples. The error is then used to steer the control voltage of the VCO. This alleviates the need of PFD and charge pump altogether. While in a phase detector that is based on chopping and correlated double sampling is used to minimize mismatches.In all of the published techniques, a select logic block generates the SEL pulse that opens the aperture for reference injection. These prior works assumed that the SEL pulse could be generated quickly enough to select the next reference edge. Moreover the position of the SEL pulse with respect to the Ref edge was overlooked as a possible factor to affect the pattern jitter. As can be seen from Fig. 4.6 the SEL pulse is asserted when the DIV signal goes high and then OUT1 signal, one of the VCO phases, goes high. The delay for generating the SEL signal from the time the VCO signal OUT1 goes high is thus equal to the delay of the CMOS level restoration buffer after OUT1, not shown in Fig. 4.6, plus 3 or 4 gate delays inside the select logic. This has to be shorter than half a clock cycle of the VCO frequency. This delay is also function of process, voltage and temperature variations. A simulation that shows the impact of the SEL pulse phase shift is illustrated in Fig. 4.7. When the SEL pulses arrives early with respect to the VCO and reference edges, a hold violation inside the select multiplexer causes significant period jitter in the VCO output. Similarly, a SEL pulse arriving late would cause a VCO setup violation inside the multiplexer and also a period jitter increase. This constraint made the design of MDLLs for multi-gigahertz applications quite a challenging task. In fact, none of the published MDLLs, as far as we know, exceeded 2GHz operation. Figure 4.8 shows the schematic of the MDLL with the proposed modification. A 360o phase rotator uses the quadrature phases of the VCO to vary delay of the SEL pulse by 1 complete clock cycle. This can compensate for any amount of latency in the select logic generation and precisely positions the SEL pulse with respect to the ref edge to minimize the period jitter. The VCO comprises 4 delay stages.

The MUX stage is configured as a delay cell and used as the third stage of the VCO to maintain the quadrature nature between the two halves of the VCO. By doing this we can have constant phase steps for the SEL pulse tuning. The output of the phase rotators is then connected to the divider and the select logic to generate the required SEL signal. A calibration loop based on a search algorithm reads the duty cycle error of the VCO output and uses this reading as a measure of period jitter. This represents the optimal aperture position. Design of the phase rotator is shown in the inset of Fig. 4.8. The interpolator comprises a bank of capacitors, connected from one terminal together to form the interpolation node,and from the other terminal each capacitor is connected to a pair of digitally controlled pass gates. Each pass gate is connected to one of the clock inputs CLKI and CLKQ. Interpolation takes place at the common terminal of the capacitors bank as a weighted sum of input clock voltages. Because summation takes place with passive components,cannabis drying rack this implementation provides better linearity performance than the conventional current-source based phase interpolator. Conventional phase interpolators suffer from nonlinearity due to finite output impedance of current sources and clock feedthrough from input to output. A 4fF/unit capacitor is used to achieve the 4-bit matching requirement for the phase interpolator. Charge pump is a critical component of this design. Any mismatches in the charge pump will be interpreted as phase mismatches between reference and divided edge. Unlike PLLs, phase mismatches in MDLL are manifested as period jitter. The charge pump used in this design minimizes static and dynamic mismatches to less than 0.5%, which was satisfactory for our application. Fig. 4.9 shows the charge pump design. Static mismatch is corrected by Transistors M1-M4, which form a singled ended replica of the charge pump. Amplifier 1 forces the output node of the replica to be equal to the control voltage by changing the down current. This guarantees that the DC up and down currents of the charge pump are equal . It also guarantees that the down current is tracking the up current with different control voltages. This means that the charge pump can be used with wider control voltage ranges and therefore lower VCO gain. Using a voltage follower amplifier connected between VCTRL and VCTRL1 is used traditionally to minimize dynamic mismatch. Keeping VCTRL1 equals to VCTRL reduces charge sharing caused by switching currents between these 2 nodes. In our design, dynamic mismatch is corrected by another replica charge pump M5-M10. This replica guarantees that current is always flowing through the charge pump branch formed by M13-M14. This branch now is identical to the single ended replica and node VCTRL1 remains equal to VCTRL. Current consumed by this replica is tens of microamperes. To minimize area, the MDLL loop filter capacitor is implemented using core thin-oxide devices rather than thick oxide devices. This reduces loop filter area by 63%.

Due to the high gate leakage of these devices, an additional compensation technique similar to is used. Amplifier 2, M17 and a replica of the loop filter capacitor are connected in a negative feedback configuration as shown in Fig. 4.9. The loop sets M17 current to be equal to the replica capacitor leakage. Consequently, the leakage current in the loop filter is provided by M18 instead of leaking the charge on the loop filter capacitor.The noise analysis in chapter 3 and section 4.1 ensures the clock propagates across the entire cable length with sufficiently low noise. For data transmission, the distance between data repeaters is essentially a point-to-point link. The primary constraint is to minimize the power/meter for the targeted data rate. Longer repeat distances reduce power/meter by amortizing the repeater circuit’s power. However, with more channel attenuation, more power is needed for equalization. For this study, CAT7 cable is used which has approximately 2.2-dB loss per meter at the data Nyquist frequency of 6GHz. This power trade-off with distance is analyzed and illustrated in Fig. 4.10. Total energy per bit for repeated data transmission across 100 meters is shown versus section repeat distance. Short distances require no equalization but pays the power penalty of terminating the cable for a given minimum receiver sensitivity. Modest equalization power is possible if data repeat distance is kept below 20dB channel loss, which is equivalent to 9m of CAT7 cable. Channel loss beyond this requires added filtering which increases the power per repeater. This analysis uses realistic circuit simulations and includes varying the driver power for higher signal swing to compensate for cable loss. A shallow optimum exists between 4 and 8 meters. An 8-m data repeating distance is chosen to minimize the cost of inserting a large number of repeaters. Figure 4.11 shows the transceiver block diagram of each repeater. The transmitter uses a half-rate architecture and comprises a 16-1 data serializer. The delay for the pre-emphasis FIR is performed in the low frequency digital section to save power. The CML driver has 1 precursor and 2 post-cursor pre-emphasis taps to achieve 9 dB of equalization. The pattern generator and the serializer are used to generate data at each repeater for signal quality and BER characterization.